Envelope tracking (ET) and digital predistortion (DPD) coefficients of an electronic device being calibrated, referred to as a device under calibration (DUC), are determined using a calibration process referred to as “ET calibration.” An example of a typical DUC is a power amplifier (PA) circuit, which includes a PA having a non-linear response to an input stimulus signal. Conventional ET calibration methods include a test bench method, according to which output signals of the DUC are measured in response to application of high-power continuous wave (CW) signals over extended periods of time, a situation not representative of normal product use, and not in line with how the product is best optimized in computer-aided design.
The test bench method is based on simplistic views of an envelope tracking PA (ETPA), for example, and do not result in calibration of the ETPA circuit that produces optimum overall performance. Generally, there are two sets of issues in optimizing calibration of an ETPA circuit (i.e., the DUC). First, it is assumed that an optimized ETPA circuit should have a bias shaping function (SF) based on power gain. With phase-only DPD, it is assumed that this power gain should be constant to minimize distortion. With full amplitude and phase DPD, a constant gain compression (e.g., 2-5 dB) thought to be associated with best efficiency is often used. SF coefficients are often determined based on mid-band power gain. Such approaches lead only to initial guesses for an optimum SF. Gain is not constant across the band, so a midband-based choice does not necessarily produce the best compromise. A constant level of compression is not fundamentally optimum, and the necessary tradeoffs to meet other specifications are not addressed. ET and DPD provide relief in the classical tradeoff of efficiency for linearity, but other tradeoff quantities remain, such as gain; and a new key one is introduced: the power and modulation-bandwidth dependent efficiency of the ET bias modulator (ETBM).
Second, in order to determine the SF coefficients during calibration, high-power CW signals are applied to the ETPA circuit, including at high powers, over a period of time much longer than the ETPA circuit would experience in the field. This extended application of high power CW signals may result in damage to sensitive components of the ETPA circuit. At the time of calibration, the DUC has been invested with nearly all of the value added by manufacture. Therefore, damage caused by calibration is especially costly, be it due to yield loss in a final screening test or in increased number of field returns.
Accordingly, what is needed is a method to determine optimized calibration parameter values of a DUC without applying potentially damaging high-power CW signals over extended periods of time while also avoiding the overly-restrictive constraints that conventional methods commonly employ. The illustrative embodiments of the disclosure provide methods that address these needs with an approach proven in the DUC design phase.